1. Field of the Invention
This invention relates to computer storage systems, and more particularly to a computer storage system having a dual port buffer memory for improved performance.
2. Description of Related Art
A typical data processing system generally includes one or more storage units connected to at least one central processor unit (CPU). The function of the storage units is to store data and programs which the CPU uses in performing particular data processing tasks. Various types of storage units are used in current computer systems. A typical computer system may include one or more large capacity tape units and/or disk drives (magnetic, optical, or semiconductor).
Recently, disk array systems of various types have also been used to provide data storage for computer systems. Disk array systems comprise a plurality of storage units coupled in a redundant configuration such that the failure of any one storage unit will not cause a loss of data. A research group at the University of California, Berkeley, in a paper entitled "A Case for Redundant Arrays of Inexpensive Disks (RAID)", Patterson, et al., Proc. ACM SIGMOD, June 1988, has cataloged a number of different types of disk array systems by defining five architectures under the acronym "RAID".
In many modern computer architectures, the CPU does not directly control attached storage units. Rather, the CPU is coupled to a storage subsystem independently controlled by a storage unit controller. A local microprocessor unit (MPU) in the storage unit controller accepts data requests (e.g., READ or WRITE commands) from a CPU and thereafter controls the storage unit subsystem to execute the command while the CPU performs other functions.
An advantage of a storage unit controller is the ability of the controller to keep large numbers of relatively slow mass storage units busy a high percentage of the time. This is particularly important with respect to redundant array storage systems, because failure to keep all of the storage units active results in an under-utilized resource. Therefore, the MPU must always be able to provide any available storage unit with a task in order to achieve the highest performance efficiency.
Accordingly, the prior art has taught the use of a large buffer memory coupled to both the CPU and to the storage units in order to disconnect storage unit activity and CPU activity by "staging" data between the two. FIG. 1 is a block diagram of a typical prior art configuration in which a CPU 1 is coupled via a CPU bus 2 to a CPU interface 3 that is part of the storage subsystem. An internal bus 4 within the storage subsystem couples the CPU interface 3 to an MPU 5, a buffer memory 6, and a storage unit interface 7. If the storage subsystem uses a redundant array storage system, a plurality of storage units S1-S5 are coupled to the internal bus 4 through the storage unit interface 7 (five storage units are shown by way of illustration only).
During a WRITE operation, data from the CPU 1 is transferred through the CPU interface 3 and internal bus 4 to the buffer memory 6. Once an entire transaction is stored in the buffer memory 6, the data subsequently is transferred from the buffer memory 6 to the storage units S1-S5 through the storage unit interface 7.
During a READ operation, the reverse path is taken: data from the storage units S1-S5 is transferred through the storage unit interface 7 into the buffer memory 6. Once an entire transaction has been transferred to the buffer memory 6, the data subsequently is transferred from the buffer memory 6 through the CPU interface 3 to the CPU 1.
The buffer memory 6 serves to match the transfer speed of the CPU to the transfer speed of the storage units. Also, in the case of a disk array storage system, the buffer memory 6 is used as a distribution point during WRITE operations and as a collection point during READ operations so that the CPU 1 never sees the data is actually distributed among the plurality of storage units S1-S5 (i.e., data from the CPU may be split among the storage units).
A major disadvantage of the prior art architecture is that data must cross the same data bus twice: once between the CPU 1 and buffer memory 6, and again between the buffer memory 6 and the storage units S1-S5. This characteristic effectively cuts the data bus bandwidth in half, thereby reducing performance of the storage subsystem.
Therefore, a need exists for improving the performance of storage subsystem, and especially redundant array data storage subsystems. In particular, a need exists for providing a higher effective data bus bandwidth in such storage subsystems.
The present invention provides a solution to these problems.